Semiconductor integrated circuits (ICs) are typically manufactured using a series of deposition, implantation, and annealing steps to form desired regions and junctions within a semiconductor wafer. Implantation is premised on the theory of implanting different elements in a wafer using different energy levels, doses, and angles to achieve the optimum dopant concentration and junction depth in a wafer. An implant dose is determined by the beam current applied to ionize the elements to be implanted, implant time, and beam diameter. A higher beam current ionizes more particles, resulting in a higher implant dose concentration. Implant depth is controlled by varying the implant energy and/or angle. To achieve deeper junctions, higher energy levels and/or angles that allow channeling are used. Channeling is the phenomenon whereby implanted ions travel easily through specific crystallographic orientations.
As IC technology advances, multiple ion implants are becoming more prevalant to allow detailed engineering of doping profiles, which optimizes transistor and other IC device performance. Currently, to perform such multiple implants, implantation equipment stops the implantation beam current after each particular energy and dose. This is done either with or without removing the wafers from the chamber. The implant dose, energy, and/or angle are then changed prior to restarting the next implantation. This unduly burdens the manufacturing process due to the added overhead and cost associated with such downtime.
As a result of such high costs associated with changing implant dose, energy, and/or angles, device designers are forced to use fewer implants. Instead, they must use more DT (i.e., a combination of time spent in a furnace and the temperature at which the furnace is set). DT is needed to merge implants together by diffusing implanted ions through the wafer, a process which ideally is performed by using multiple implants to create such profiles.
It is undesirable to rely so heavily on DT to obtain desired impurity profiles. DT degrades steep implant profiles that are often crucial in ICs. A conventional doping profile is shown in FIG. 1A, resulting from three separate implants. The number of dopants, N, is plotted versus the depth, X, in a wafer. FIG. 1B, shows the effects of a 1,050 to 1,150 degrees Celsius DT for two hours used to obtain a final doping profile. As ICs are scaled down, steep implant profiles are even more critical to optimized device performance because there is less area within which to obtain desired dopant density variations necessary for proper device performance. As can be seen from FIG. 1B, previous techniques of forming doping profiles do not result in steep, sharply defined profiles. Furthermore, DT often results in significant lateral spread of the implanted dopants, undesirably decreasing achievable integrated circuit (IC) density.
Another problem with relying so heavily on DT is that it reduces valuable thermal budget required for many process steps needed for forming ICs. The thermal budget for a particular device is the amount of time and temperature that the device can withstand before device performance is degraded. Many process steps reduce the remaining thermal budget. It is thus critical to conserve thermal budget when possible.
There is a need for a technique for implanting semiconductor wafers which allows for efficient multiple implants. There is a need to decrease the amount of overhead and cost associated with changing implantation energy, dose, and/or angle between such implants. It is further desirable to decrease the amount of DT, which is currently used and needed, for forming doping profiles in semiconductor wafers. A technique for forming steeper, sharply defined doping profiles is needed in order to keep pace with performance standards required of ever shrinking device geometries in today's ICs.